This invention relates to input/output (I/O) drivers for integrated circuits, and more particularly to a technique for enhancing the output drive of I/O drivers in integrated circuits whose supply voltages are lower than the operating voltages associated with the I/O standards being supported.
Continuing advances in semiconductor process technology have contributed to the proliferation of I/O standards with ever-lower operating voltages. In particular, as critical feature sizes for MOS processes are scaled down to achieve greater densities and performance enhancements, the supply voltages are often scaled down proportionally to decrease power consumption and to avoid reliability problems.
For integrated circuits that are used in a wide variety of applications (e.g., programmable logic devices), reliable interoperability with systems employing different I/O signalling voltages has become an important design consideration as a result of this trend in power supply scaling. A variety of design considerations relating to interfacing devices in mixed-voltage environments, such as handling overvoltage conditions and producing compatible signalling levels, are addressed in commonly-assigned U.S. Pat. Nos. 6,147,511 and 6,118,302, both of which are hereby incorporated by reference herein in their entireties.
Often, an integrated circuit fabricated in the most current process will have to support I/O standards from earlier generations, thereby interfacing with I/O voltages that are, most likely, higher than the associated core supply voltage and/or the associated I/O supply voltage of that integrated circuit. As a consequence, the transistors comprising the I/O circuitry will often have thicker gate oxides than those in the core circuitry in order to operate more reliably with I/O voltages that may be higher than the internal supplies.
Although thick oxide transistors may reliably operate with a wider range of signalling voltages, the thicker gate oxide layer may degrade the output drive of these transistors. For NMOS transistors, increasing the gate oxide thickness may further aggravate the problem of reduced output drive arising from the ever-lower logic HIGH gate drive signals available as a result of power supply scaling. The decrease in output drive can be offset by using larger transistors; however, this option is not always desirable as it may increase the size of the chip.
It is therefore an object of this invention to provide a technique for enhancing the output drive capacity of the output drivers on an integrated circuit supporting I/O signalling levels that are higher than the supply voltages of that integrated circuit without resorting to increasing the size of the output driver transistors.
A representative output driver that is to be improved in accordance with the present invention is typically found in an integrated circuit, preferably fabricated in a MOS process, that supports I/O signalling levels higher than the associated core supply voltage and/or the associated I/O supply voltage of that integrated circuit. In order to ensure that the I/O transistors can tolerate voltages higher than the intrinsic supply levels, the gate oxide layers of these transistors are often thicker than that of the transistors comprising the core circuitry.
In accordance with the present invention, a preferred way of enhancing the output drive of output drivers comprising thick oxide transistors is to level-shift the logic HIGH pull-down signals that are applied to the gates of the pull-down transistors in the output drivers, preferably to the higher termination, reference, or signalling voltage associated with the I/O standard being supported. This higher external voltage is preferably provided to the level-shifting circuitry through any spare or unused pin (e.g., I/O pin, reference pin, power pin, etc.).